The invention is directed toward the field of digital-to-analog converters (DACs) and delay-locked-loops (DLLs), and more particularly to DACs and DLLs based upon an escalator code.
Recent integrated circuits attached to a printed circuit board (PCB) e.g., synchronous DRAM (SDRAM), RAMBUS DRAM, etc. include a delay-locked-loop (DLL) circuit. The DLL circuit maintains a predetermined phase relationship between an internal clock and an external reference or system clock, e.g., supplied by a memory controller.
In its simplest form, a DLL has a programmable delay line and some control logic. The delay line produces a delayed version of the reference clock signal. The delayed clock signal is provided to the other internal circuitry of the integrated circuit, e.g., the DRAM integrated circuit (IC), of which the DLL is a part. In addition to being provided to the other internal circuitry of the IC, the internal clock signal is also fed back to delay control logic of the DLL. The delay control logic compares the clock signal which has been fed back against the reference clock signal in order to adjust an amount of delay to be caused by the programmable delay line.
FIG. 1A depicts a DLL according to the Background Art. The DLL 100 receives a reference clock, REFCLK, which is provided to a variable delay line 110. The delayed clock signal, CLKOUT, is output to the remaining circuitry of the IC (not shown). The output clock signal CLKOUT is also fed back via replica delay unit 140 as signal FBCLK to a phase comparator 130, which also receives the reference clock REFCLK. The phase comparator 130 provides an up/down-count signal to a delay control circuit (DCC) 120. The DCC 120 includes a counter 122 which provides an N-bit output to an N-bit digital-to-analog converter (DAC). The DAC 121, and therefore the DCC 120, outputs a delay adjustment signal DLYADJ to the variable delay line 110.
The function of the DLL 100 is to achieve a predetermined amount of phase difference between the reference clock signal REFCLK and the output clock signal CLKOUT. For the sake of simplicity, the operation of the DLL 100 will be explained under the assumption that the amount of predetermined delay is 360xc2x0 or one cycle. The operation of the DLL 100 will now be discussed in terms of the waveforms of FIG. 1B. In FIG. 1B, a waveform of the reference clock REFCLK is plotted. Below the REFCLK waveform, the feedback clock FBCLK waveform is plotted. As expected, the feedback clock FBCLK is delayed in phase, i.e., shifted to the right, relative to the reference clock REFCLK waveform. Recalling that the predetermined phase is assumed to be one cycle, arrows 160-168 have been provided to emphasize the delay between the rising edges of the feedback clock FBCLK waveform and the rising edges of the next respective cycle in the reference clock REFCLK waveform. Inspection of FIG. 1B reveals that the effect of the DLL 100 is to shorten the delays indicated by the arrows 160-168.
The up-count waveform and down-count waveform of the phase comparator 130 are also depicted in FIG. 1B. Each of the arrows 160-168 indicates that additional delay is needed, albeit in lesser amounts for waveform 160 through waveform 168. Hence, the durations of the square pulses 170-178 in the up-count waveform diminish from pulse 170 through pulse 178.
The phase magnitude between the feedback clock signal FBCLK in the reference clock signal REFCLK is also plotted in FIG. 1B. Inspection of the phase (PH) waveform reveals that the magnitude of the phase difference decreases with the progression through the pulses 170-178, as indicated by upward arrows 180-188. Similarly, the delay adjust DLYADJ output by the N-bit DAC 121 increases inversely proportionally to the decrease in the phase difference. Similarly, the delay waveform, namely the waveform describing how close to a full cycle is the delay, decreases from left to right in correspondence to the decrease exhibited by the arrows 180-188 of the phase PH waveform.
The DAC 121 can be implemented in a number of ways. As simple implementation is to assign binary weighting to the individual transistors within the DAC 120. FIG. 3 is a schematic block diagram of a binary-weighted DAC 300 according to the Background Art. The DAC 300 includes four 1-bit converters 302, 306, 310 and 314, which reflects an assumption of a 4-bit weighting system (the number four is chosen for simplicity; typical DACs involve more bits). The 1-bit converter 302 includes an output transistor 322 having a channel whose width-to-length (W/L) ratio is such that it produces a unit current of magnitude, i. The 1-bit converter 306 has an output transistor 324 whose channel has a width-to-length ratio of 2W/L that can sink a current of magnitude to 2i, i.e., twice that of the converter 302. The 1-bit converter 310 has an output transistor 326 whose channel width-to-length ratio is 4W/L, which can sink a current of magnitude 4i. And the 1-bit converter 314 has an output transistor 328 whose channel width-to-length ratio is 8W/L, which can sink a current of magnitude 8i.
A binary system, like any positional number system, represents a number based upon the combination of individual bits, where each bit represents a sub-value based upon its relative position and whether it is in the zero state or the one state. A 4-bit binary number has bits b3 b2 b1 b0, where b0=20=1, b1=21=2, b2=22=4 and b3=23=8, i.e., b3=8b1, b2=4b1 and b2=2b1. Inspection of the 1-bit converters 314, 310, 306 and 302 reveals that their respective currents reflect a binary weighting for a 4-bit binary number.
The DAC 300 further includes a buffer 320. One output 318 of the buffer 320 is connected to the inputs 304, 308, 312 and 316 of the 1-bit converters 302, 306, 310 and 314, respectively. Based upon the control signals applied to each of the 1-bit converters, namely b0 and b0b for converter 302, b1 and b1b for converter 306, b2 and b2b for converter 310, and b3 and b3b for converter 314, each of the 1-bit converters is selectively turned on or off. When turned on, each 1-bit converter sinks its respective current. If all of the transistors are turned on, they collectively draw the sum of their individual currents out of the buffer 320 on the output line 318. Similarly, the second output line 321 of the buffer 320 outputs the same amount of current as is drawn out of the output line 318. The current on the second output line 321 represents the delay adjust signal DLYADJ.
FIG. 2A is a depiction of an example amount of delay between the clock output CLKOUT of the DLL 100 and the reference clock REFCLK. Inspection of the waveform DLY reveals that it is a typical damping curve that settles down to a predetermined amount of delay 208. It is to be noted that the output clock CLKOUT is an analog signal that can vary continuously. In contrast, the delay control circuit (DCC) 120 is a digital device that translates the up/down control signal from the phase comparator 130 into a binary-weighted word. Due to a variety of reasons, e.g., thermal fluctuation, system voltage fluctuations, noise, etc., there will be some oscillation or jitter 210 in the delay waveform DLY even after the DLL has achieved a locked state, i.e., after the waveform DLY settles at the predetermined amount of delay 208. This jitter 210 falls within a range of values 220. The locked status of the DLL 100 is shown as being achieved after 4 xcexcsec.
FIG. 2B is a depiction of 6-bit binary words and their decimal equivalent. To simplify the explanation, it is assumed that the jitter 210 corresponds to the count values 3110 and 3210 output by the counter 122. In other words, it is assumed that the count values corresponding to the jitter 210 are 3110 and 3210. Inspection of FIG. 2B reveals that the transition from 3110 to 3210 involves a state change in each of the bits b0-b5. As the count value cycles (or jitters) between 3110 and 3210, each of the bits b0-b5 repeatedly change back and forth between a state of zero and a state of one.
When any of the bits in the count output by the counter 122 changes from one to zero or from zero to one, current either stops flowing or begins to flow through the corresponding transistor(s) of the respective 1-bit converter. If only the transistor corresponding to the least significant bit turns on or off, the difference in current can be negligible. But if all of the transistors change their conduction station, as in the transition from 3110 to 3210 or 3210 back to 3110 show in FIG. 2B, then large amounts of current are involved.
FIG. 2C depicts current amounts for a theoretical situation in which all of the transistors turn on or off, respectively, i.e., a multi-bit transition. There, the x-axis corresponds to time and the y-axis corresponds to current. Line 240 depicts the total current that switches off at the multi-bit transition time 246 while line 242 plots the total current that switches on at the transition time or point 246. Line 244 plots the summation of lines 240 and 242. In this theoretical condition, the amount of current turning off substantially equals the amount of current turning on, hence there is little to no change in the total amount of current involved.
FIG. 2D plots realistic values for the current amounts associated with the multi-bit transition point 246. Line 246 corresponds to line 240 in that it depicts the total amount of current being switched off at the multi-bit transition point 246. Line 250 corresponds to line 242 in that it plots the total amount of current being turned on at the multi-bit transition point 246. Inspection of lines 248 and 250 reveal that their transitions are very gradual in comparison to the abrupt transitions of theoretical lines 240 and 242. Line 252 corresponds to line 244 in that it plots the summation of the current represented by lines 248 and 250. Inspection of line 252 reveals that there is a significant decrease in the total current associated with the multi-bit transition point 246. This is a sharp contrast to the essentially flat line 244 of the corresponding theoretical situation.
The large change in total current passing through the DAC 121 during a multi-bit transition, as exhibited by the line 252 of FIG. 2D, generates a great deal of noise in the integrated circuit. This is a problem. When the DAC 121 is forced to cycle repeatedly through a multi-bit transition, e.g., from 3110 to 3210 and 3210 back to 3110, the problem is significantly worsened.
The Background Art attempted to deal with this problem by basing the digital-to-analog converter (DAC) 121 on a different code rather than the simple binary-weighted code. In particular, a hybrid of a binary-weighted code and a thermometer code was adopted. In the hybrid code, a number is represented in part by a binary-weighted code and in part by a thermometer code. In a thermometer code, each bit represents a predetermined decimal value.
FIG. 4A is a table of an example hybrid thermometer/binary code. There the least significant bits correspond to the binary code portion, namely bits c0 and c1. The more significant bits are represented by the thermometer code portion, namely bits b0, b1, b2 and b4. The hybrid code of FIG. 4A assumes, for simplicity, a situation in which it is only desired to represent a maximum of 1910.
Inspection of the rows in FIG. 4A corresponding to the numbers 010-310 reveals that the thermometer code has all zero values while the binary code portion exhibits a typical binary progression. At the number 410, the binary code portion resets to zero while the b0 bit of the thermometer code takes on a value of one while bits b1-b3 remain at zero. Inspection of the progression from 410-710 reveals that the binary code portion increments again through the normal binary progression while the thermometer code portion remains the same. At the number 810, however, the binary code portion resets to zero while the b1 bit of the thermometer code takes a value of one. Inspection of the progression from 810 through 1110 again reveals that the binary code portion undergoes the normal binary progression while the thermometer code portion remains the same. At the number 1210, the binary code portion resets while the b2 bit of the thermometer code portion changes to a value of one.
FIG. 4B is a schematic block diagram of a circuit for generating the hybrid code of FIG. 4A, according to the Background Art. Up/down count signals (from the comparator 130) are received by a 4-bit counter 410. The upper two most significant bits c3, c2 are provided to a thermal decoder 420, which outputs a 4-bit thermometer code b3b2b1b0.
FIG. 4C is a schematic block diagram for a DAC 430 (according to the Background Art) based upon the hybrid code of FIGS. 4A-4B. The DAC 430 includes six 1-bit converters 4311, 4312, 4313, 4314, 4321 and 4322. The 1-bit converter 4321 has a W/L ratio that can be considered to produce a unit current having a magnitude known as i. Consistent with a binary weighting, the 1-bit converter has a ratio of 2W/L for a current capacity of 2i. The four 1-bit converters 4311-4314 each have the same ratio, namely 4W/L for a current capacity of 4i. The converters 4321 and 4322 receive the outputs c0-c1, respectively. The converters 4311-4314 receive the outputs b0-b2, respectively.
In terms of multi-bit transitions, the hybrid code of FIG. 4A exhibits a worst-case scenario at the transitions between 310 and 410, 710 and 810, 1110 and 1210, and 1510 and 1610. But it is to be noticed that only 3-bits change during those transitions, namely the binary code bits c0 and c1 and only one of the thermometer code bits. Consequently, the DAC based upon the hybrid code exhibits a much smaller change in total current during a multi-bit transition than does the purely binary-coded type of DAC. This is an advantage conferred by the thermometer code aspect of the hybrid code.
But the thermometer code aspect also confers some disadvantages. In order to keep the binary code portion to a relatively small number of bits, each bit of the thermometer code can be represent a relatively small decimal equivalent. In the example of FIG. 4A, each bit of the thermometer code portion represents the number 410, which corresponds to 22. Consequently, in the hybrid code of FIG. 4A, the binary code portion is kept to a mere two binary bits c0 and c1. If the binary code portion were increased to 3-bits so that the most significant bit in the binary code portion had a value representing 22=410, then each bit in the thermometer code would represent the next higher power of 2, namely 23=810.
This relationship is important because the number of thermometer code bits needed to represent a particular value increases as the decimal equivalent represented by each thermometer bit decreases. In the example of FIG. 4A, the hybrid code could represent only a maximum of 1910. This is a small number and yet it requires a 4-bit thermometer code. As such, a problem with using the thermometer code is that it typically requires a great many bits to represent a reasonably large number. Consequently, the corresponding transistor circuitry consumes a great deal of surface area on an integrated circuit and its wiring significantly complicates the architecture of the DAC of which it is a part.
Among others, an embodiment of the invention provides a digital to analog converter (DAC) (and corresponding method) comprising: an escalator code generator, responsive to an externally-provided count trigger signal, to generate an escalator code; and an escalator-code-to-analog converter (ECAC) to convert said escalator code from said generator; wherein said generator is arranged to (1) represent base 10 numbers with a mixed code having a coin code portion and a cash code portion so as to eliminate multi-bit changes in the cash code portion upon changes in count direction, said coin code corresponding to one or more of the least significant bits of said cash code but fewer than all bits of said cash code; and (2) represent a count in a first direction as a summation of the base 10 number represented by said coin code and the base 10 number represented by said cash code; wherein said generator is operable to alter said coin code when said count changes direction while said cash code remains the same until a count capacity of said coin code is exceeded, said cash code being alterable after said count capacity of said coin code is exceeded; wherein cycling between adjacent base 10 numbers is manifested in said coin code portion while keeping said cash code portion the same; and wherein noise introduced into an output of said ECAC due to such cycling is reduced because said cycling is manifested in said coin code portion.
An escalator code generator according to an embodiment of the invention can include a coin code counter and a cash code counter. The coin code counter is for counting a value of a coin code, and can operate in response to count-up and count-down signals UP and DN outputted from a phase detector. The cash code counter can operate in response to output signals S1 and S0 from the coin code counter and the count-up and count-down signals UP and DN from the phase detector. That is, the coin counter receives count pulses from the phase detector to output a 2-bit coin code S[1:0]. A coin counter has any one of 00, 01, and 11 states based on count pulses. When the coin counter reaches the 11 state, i.e., full state, the count-up signal UP cannot increase the value in the coin counter but can increase the value in the cash counter.
For example, after the coin counter reaches the 00 state, i.e., empty state, the count-down signal DN cannot decrease the value in the coin counter but can decrease the value in the cash counter. The cash counter receives a count pulse from the phase detector and a coin code S[1:0] from the coin counter to output a cash code B[7:0]. When a coin code is in a full state (and cannot be increased), then a state of the cash counter is increased to the next state based on the count-up signal UP. But when the coin code is in an empty state, the state of the cash counter is maintained while a state of the coin counter is increased in response to a count pulse. The coin counter is sufficiently large that bang-bang jitter (or cycling or ringing) occurring during a synchronization state of a delay locked loop (DLL) will not cause a change in the value of the cash counter. In other words, the repetition of the count-up and count-down signals UP and DN, caused by the bang-bang jitter, can vary the value represented by the coin code and but will not disturb the value in the cash counter. For example, if a magnitude of the bang-bang jitter is within a second weight of the cash counter, a magnitude of the coin counter can be equal to a second bit of the cash counter 224.
Additional features and advantages of the invention will be more fully apparent from the following detailed description of example embodiments, the appended claims and the accompanying drawings.